COURS PROTOCOLE HDLC PDF
PROTOCOLES DE ROUTAGE: pour rôle l’échanges des informations de routes calculées par les Tâches d’une passerelle IP. Pour chaque datagramme IP qui traverse une passerelle, le protocole IP: . Niveau 2: HDLC. Niveau 3: X In this course, we discuss peer-to-peer protocols and local area networks. Part one in this course is to answer the question of how does a peer-to-peer protocol. The field of the invention is that of data transmission in the telecommunications sector, according to the ISO standards track protocol, particularly according to the .
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Kind code of ref document: Country of ref document: Date of ref document: Ref legal event code: Year of fee payment: The field of the invention is that of data transmission in the telecommunications sector, according to the ISO standards track protocol, particularly according to the levels 1 and 2 of the standard.
However, of course, the scope of the invention extends to other embodiments, in which one can find a level of frame 2 ISO format replacement of HDLC combined with a multiplexing mode more formatted channels on the transmission link Alternate MIC.
Coding HDLC is to serialize the data and format in successive identifiable frames, each comprising, in particular, a “flag” fields separation signal, and a control information on two bytes, of the validity of the frame signature established as a function of bits of the framerecalculated on reception. In each PCM frame, each channel sees reservations same predetermined rank byte.
The insertion of the HDLC frames in the PCM format to the transmitter, then the receiver frames recovery entails having at each end of the chain of transmission of a specific system.
The invention relates to the receiving part of such a system. Are already known HDLC frame receiving systems transmitted over such channels MIC, comprising either a machine specialized from slice processors or a plurality of processors each assigned to a channel of the PCM link.
Thus, in the known system shown in Figure 4, is carried out the recovery of HDLC frames, channel by channel, after demultiplexing This is achieved by means of a specific line for each of the channels, comprising firstly a HDLC circuit own 41, and secondly an own processor 42 associated with a buffer memory Each of the lines 44 corresponding to a distinct channel feeds a common memory remultiplexing 47 which concentrates the decoded frames 48 before they are transmitted on a 50 processing bus 49 with processor 3 ISO level.
The existing system is fully operational, but has the disadvantage of the multiplication of components as many components as assaultand management resulting complexity. These drawbacks are particularly disadvantageous for the development of switching systems to manage a very large number of lines carrying large flows of digital data.
Until recently, in fact, the PCM links channel acheminaient just some logical channels 2 for examplethe other channels are analog. Lrotocole it was possible, even necessary, to deal separately with each channel, the multiplication of components 41, 42, 43 on several parallel tracks only offset by the permitted and coyrs flexibility.
It is known, in this direction, to perform the functions of the circuit hdkc, for couts channels multiplexed in time, using a single circuit multiplexed channels having a state memory, and the receipt of a byte from each channel in a frame, reading from the memory the state of the channel stored in the previous frame, in order to resume processing of the track, as it had been left after the receipt of a byte of that channel in the preceding frame.
With respect to the diagram of Figure 4, such a single multiplexed HDLC circuit would be placed before the demultiplexer 45, instead that there is one for each channel placed after the demultiplexer. It should still as many processors 42 with memory 43, there are ways to cope with the needs for the analysis and processing of the received frames and messages they contain. The invention aims prootocole provide an HDLC frame receiving system transmitted over PCM channels comprising means, common to all channels, analysis and processing of the frames, so as to avoid duplication of identical material means each channel, taking into account that each frame must undergo specific treatment.
Another object of the invention is to provide such a system for receiving and processing frames, together with a standard processor, reduces the execution time of repetitive frames of analysis. Another object of the invention is to provide such a system allowing a variable processing time for the received data.
cours protocole hdlc pdf to word
The invention also aims to provide for such a system, a wired device, simple design, fast operation, and supports the cohabitation of different procedures simultaneously on the PCM channels eg CCITT n7 and X Advantageously, said transcoding means cooperating with said controller comprising: In this way, the said machine, exempt from the prior analysis of the information concerning the circumstances of the transmission, as well as the monitoring of the reception of the frames directly performs the processing required by the reception of each byte.
Advantageously, said status information relating to the current data comprise at least one of the following: Preferably, the analysis means and word processing includes counting means the number of bytes received for each HDLC frame received on each channel, and said number of bytes of information is supplied to said transcoding means for identifying a specific processing of each byte according to the rank of this byte in the complete frame to which said byte belongs.
Furthermore, said transcoding means also advantageously have an input for receiving status information corresponding to the occurrence of a synchronization signal, said information being supplied by said HDLC decoding means for each synchronization byte of the received PCM frame. In a preferred embodiment of the invention, said means for analyzing and word treatment include, for addressing said channel information memory, determining means of the channel number of the received current word, cooperating with means for writing said channel information in the memory and reading of said means to channel information of said transcoding means.
According to another advantageous characteristic of the invention, said information processing provided by the transcoding means is constituted by a branch address from the processing machine, thereby providing the address directly processing program to be applied on the ‘byte received.
The processing device preferably further comprises means for triggering the next cycle of the means for analyzing and processing words, after execution of the current word processing cycle. Other features and advantages of the invention appear on reading the following description of a preferred embodiment of the invention given by way of illustration and not limitation, and the appended drawings in which: The embodiment to be described hereinafter relates to a link 10 of type MIC, built from 31 HDLC channels 11 multiplexed 12 with a synchronization channel 32nd standard MIC as shown schematically in Figure 1.
The HDLC frames are transmitted successively on each channel, with a frame separator 21 between each successive frame. If no frame, transmitting continuous flags separators Of course, a symmetric component is used in the reception part, to recover the transmitted data, by performing the following functions: The data is transmitted in successive blocks of bits, being repeated endlessly, the type of the block shown in Figure 3.
This block is composed of 32 time slots 31, each of 8 bits: L’octet IT0 contient un signal de synchronisation. The byte TS0 contains a synchronization signal. Bytes IT1 to TS31 each correspond to a channel or channel of different transmission. From the point of view of the transmitter or receiver, each subscriber therefore sees its sectioned data, and transmitted every bits, multiplexing with the data from parallel tracks. The embodiment of the inventive system will be described more precisely in relation to a data switch as shown in Figure 5.
Such data switch is for example constituted by a multibus multiprocessor system wherein one can distinguish: Buses 51, 52, 53 of the system are connected to each other through pairs of bus couplers 54 which allow processor 55 connected to each bus to communicate with each other or with slave devices such as memories Connection to a PCM link 10 is effected through a PCM coupler 57 preferably connected in parallel to two buses 52, On both interfaces of the coupler 57 with the PCM bus 52, 53, only one is active at a given time, under control of an access control processor 61 Figure 6.
The activation of the second interface can for example respond to a failure of the first, the double connection of the MIC coupler 57 thus being performed for security reasons. MIC coupler is connected to two buses 52, 53 from the data switch by means of two isolation circuits 62, the type of buffer tristate circuits, controlled by the control processor Le processeur de gestion 61 comporte en outre d’autres fonctions: The management processor 61 also includes other features: MIC coupler further comprises firstly a local memory 63, and secondly two processing branches 64, 65 respectively corresponding to the receiving module and the coupler transmitting module.
Each module 64, 65 comprises, firstly, a processor 66, 67, and secondly an HDLC circuit 68, 69 comprising functions “USART” to the issue or receipt, as described above.
The invention relates more particularly to the structure and operation of the module 64, for receiving frames of HDLC operations transmitted on the PCM link Figure 7 shows diagrammatically the assembly of the main elements of the receiving systems of the invention.
On peut y distinguer: The operation means 70 for HDLC decoding is as follows. As already noted, the PCM link supports 32 time intervals. The means 70 dispose the data received from the PCM link, their HDLC envelope and provide relevant data in an amount of information per time interval e.
More specifically, the hclc 70 emit each received PCM frame, one byte 71 for each of the 32 channels of the PCM link. Consequently, the means 70 operate as follows: A word consists of one byte of data 71 fraction frame accompanied by a status information 72 specifying the nature of the byte.
Frame start, frame end, error, etc. The data stored in the FIFO 73 is then read by the means 74 of analysis and processing of words. An advantageous embodiment of the structure of the means 74 of analysis protkcole processing of words is shown in Figure 8.
The central element of the analysis device and processing the words is read only memory transcoding 8O. At the output, the conversion memory 80 provides information 81 of adequate treatment for the current data This processing information 81 is read together protocple the data 71 by the controller 76 which thus identifies the appropriate treatment for the outgoing data.
The transcoding memory 80 works in cooperation with the following modules: This counter 84 undergoes a reset 87 in the presence of ITO code. He suffers no advance FIFO 88 if the channel is empty, and is incremented otherwise.
L’avance a lieu en fin de cycle, ce qui permet d’employer des composants ordinaires. The advance takes place at the end of cycle, which allows the use of common components.
cours protocole hdlc pdf to word – PDF Files
The ROC field is reset ;rotocole event “end of frame or fault detected”, but protofole its value to “incomplete byte”. Taking into account protlcole rank of the current byte is used to selectively address each of the received frames as a function of its length.
The operation of the state diagram is as follows: If the length of the frame does not correspond to a possible case, the system starts in ER error processing.
A cycle of operation of the means 74 of Figure 8 begins by receiving a trigger signal LEC 95 from the controller 76, when it is ready to receive and process a received byte in one of the channels of the ckurs MIC This signal opens the switches transferring the data signal 71 and the processing information 81 in the direction of protocolf controller 76, but the information in question is not yet ready. The signal 95 also triggers the operation of a control logic courrs generates control signals necessary for the performance of a complete operating cycle of the device However, the absence of the ready signal FIFO 78 inhibits such a cycle.
The signal 95 causes a further read cycle in the memory 80 constituting the transcoding device. The address is composed, as shown, the signals 79, 72, ccours, characterizing the state or type of procedure applied to the channel concerned INFthe number of bytes received since the beginning of protocoe frame current ROCif applicable, a status information which depends on the circumstances of the delivery of the byte received or should be in the frame 90 to 93 according to the table provided beforehand, and the state, occupied or empty, the FIFO as described above.
In response, directly, the transcoding device provides the information written to this address identifier comprises dhlc processing information, as indicated above, a program which should be run on the data byte As shown in Figure 9, this information is available in the prktocole third of a time interval of ns at the expiry of which the controller 76 comes to play back. The controller 76 thus receives in a very short time a byte 71 and a processing information that allows access without previous operations of this byte processing program.
The time saving is important since, to handle bytes arriving at the rate of one byte every protocoke. One can even say that, unless you use a high-speed processor, very expensive, the controller 76 would have been unable to process 31 channels of PCM CEPT. Then when the logic 94 generates the signal 93 applied to the memory 85, 86, optionally the information incremented by the incrementer 90 is reregistered to an address which is hd,c still that of the considered channel.
The signal 96 is then generated by the logic 94 and it is applied to the input FIFO advance, commanding a reading operation regarding the next channel.
La fin du signal 96 produit le signal transitoire 88 qui provoque l’avance du compteur de voies The end of the signal 96 produces the transient signal 88 which causes the advance of the line counter prottocole System according to claim 1 characterised in that it comprises a FIFO memory 73 between said frame receiving means 70 and said word analysing and processing means System according to claim 1 characterised in that said status information 72 relating to the current data byte 71 comprises at least one of the following: System according to claim 1 characterised in that said word analysing and processing means 74 comprise means 85; 90 for counting the number of bytes received for each HDLC frame received on each channel and in that the number of bytes is supplied to said transcoding means 80 in order to identify specific processing of each byte according to the location of the byte in the frame.
protofole System according to claim 1 characterised in that said transcoding means 80 have an input for status information 72 corresponding to the occurrence of a synchronisation signal, said information 72 being supplied by said HDLC decoding means 70 for each synchronisation signal of the received PCM frame.